An Efficient Design of Sub-threshold Logic Circuits for Ultra Low Power VLSI Applications
نویسندگان
چکیده
منابع مشابه
Sub-threshold Circuit Design Techniques for Ultra Low-Power Logic
With CMOS technology being scaled to ever smaller dimensions to achieve higher performance and integration levels, power dissipation has become a major concern in modern VLSI designs. Sub-threshold circuits have gained a lot of importance due to ultra low-power consumption. The paper reviews the sub-threshold circuit design. Various body-biasing schemes and logic families for performance enhanc...
متن کاملUltra Low Power Digital Logic Circuits in Sub-threshold for Biomedical Applications
Motivated by emerging battery operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits, by operating the devices at low currents and low voltages[1,2,3,4].It is known that MOS devices and circuits especially CMOS circuits consume relatively low power[5,6] . But there seems to be a need t...
متن کاملSub-threshold Logic for Ultra-Low Power Consumption
In the ultra low power end of design spectrum when performance is of secondary importance, digital subthreshold logic circuits are more applicable than the regular MOS logic. In this paper, we propose two different subthreshold logic families: 1) variable threshold voltage subthreshold CMOS (VT-Sub-CMOS) and 2) subthreshold dynamic threshold voltage MOS (SubDTMOS) logic. Both these logic famili...
متن کاملRoadmap for nanometer ultra-low-power digital circuits based on sub/near-threshold CMOS logic
For a decade, low-power design has been part of mainstream semiconductor R&D activities, while ultra-lowpower (ULP) design remained dedicated to niche markets of particular applications such as sensor networks, RFIDs and biomedical devices, where speed performances are not critical. However, today’s 65/45nm CMOS technologies offer so compact circuits and high device performance that they give t...
متن کاملDynamic-Threshold Logic for Low-Power VLSI Design
Power dissipation is a serious concern for circuit designers. Partially-depleted SOI provides a Dynamic Threshold MOS transistor that may be useful in reducing static power and dynamic power. DTMOS can be used to choke off leakage current and improve performance of transistors under lower voltage conditions, but suffers from high bodycontact resistance, Miller capacitance, area penalties, and l...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: Indian Journal of Science and Technology
سال: 2016
ISSN: 0974-5645,0974-6846
DOI: 10.17485/ijst/2016/v9i48/106447